In the manufacture of integrated circuits, thin films of various materials are deposited onto on wafers of semiconducting material, such as doped silicon. Specific selected areas of deposited films are removed to form structures and circuitry. Physical Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD) are well known processes for depositing such thin films. For example, polysilicon is typically deposited from a mixture of silane gas (SiH.sub.4) and hydrogen. Similarly, tungsten silicide is deposited from a mixture of gases including silane and a tungsten-bearing gas such as tungsten hexafhoride. Pure tungsten is also deposited on silicon wafers in the manufacture of integrated circuits, sometimes selectively and sometimes across the entire surface in a process known as "blanket" tungsten.
Typically during fabrication of integrated circuits, where it is necessary to form electrical connection between different layers, channels called vias are etched through the layers that are usually oxide to provide access to underlying electrically conductive layers so electrical connections can be made. Electrical contact is then established with the underlying layers by coating the wafer with tungsten over the entire wafer surface to fill the vias, then etching away the excess tungsten to leave the vias filled with tungsten. The filled vias are called "plugs". Subsequent metallization and patterning can connect these plugs to allow device operation.
Via fill and etchback has been accomplished in a number of different ways. For example, a blanket tungsten CVD process can be used to fill the vias while covering the entire wafer surface with tungsten. The tungsten is then etched away until only the vias are left with tungsten.
A significant problem with the blanket tungsten approach is presented by the fact that the original topography of the wafer with vias is uneven, and the coating tends to replicate the original topography. If the etchback is initiated with an uneven topography, which may result from thick and thin films of tungsten on the same wafer, the etch proceeds unevenly as well. In this circumstance it is not possible to terminate the etch with all of the vias plugged to their full depth with tungsten. One way of combatting the uneven etch problem is to make the blanket tungsten layer thick enough to "planarize". The surface can also be planarized with a coating of a different sort, such as photoresist or silicon dioxide, before the etchback.
Another way is to use a selective tungsten CVD process which deposits tungsten selectively in the vias. In the selective process, since the vias are of different depth and often of different size and shape, the process has to be continued until all the vias are filled, so many are overfilled. The overfilled vias are called "nailheads" in the art. In this procedure the already uneven topography is made more uneven by the nailheads. To do a uniform etch with the selective approach, planarization is also necessary before the etchback step.
Even with a planar starting surface there are significant problems in etching so that all vias are filled uniformly with tungsten. One of the more serious problems is called "microloading" in the art. In the etch process, with a fixed amount of power, a relatively constant gas flow, and a relatively constant surface area of tungsten and other material exposed to the plasma, the etch proceeds evenly and smoothly. If one of the variables suddenly changes without adequate compensation of other variables, the etch rate may change drastically as well. In the blanket tungsten etch process this happens at the time in the process that the surface tungsten begins to be depleted. i.e. in the regions of thinner tungsten.
Since it is not possible to make the tungsten thickness exactly uniform over the entire wafer surface, the broad area of tungsten will disappear first at the places on the wafer that the tungsten layer is thinnest, usually near the periphery of the wafer. In these areas etching becomes concentrated and much more rapid in the vias, while on other parts of the wafer, etching is still at the slower rate. Another mechanism that contributes to the higher rates is that uncovering more oxide results in additional oxygen activation of fluorine etch species in the plasma. The end result is that some vias are properly filled and some with an excess amount of tungsten are removed. This is referred to as "microloading" in the art. Microloading can also be a problem with the selective process if all of the nailheads do not have the same height and area.
A useful article that discusses the microloading phenomenon is "Plasma Etching Methods for the Formation of Planarized Tungsten Plugs Used in Multilevel VLSI Metallizations" by R. J. Saia, et al. in the Journal of the Electrochemical Society, April 1988. This article is incorporated by reference in this specification.
A number of different approaches have been taken to compensate for the microloading problem, such as extreme care in planarization, and proceeding very slowly in etching, particularly near the end of the etch process. Other methods include a process in which a layer of silicon nitride is deposited on the wafer to act as a sacrificial material during the etchback to defeat the microloading effect. i.e. no oxide being exposed. The sacrificial SiN approach is described in an article "A Novel Blanket Tungsten Etchback Scheme" by J. M. F. G. van Learhoven et al., presented at the 1989 IEEE VMIC Conference Jun. 12-13, 1989. A problem with that approach is that the extra layer of material requires extra processing steps in the overall process flow.
What is needed is an apparatus and method to overcome the microloading effect without increasing the time for or the complexity of the etchback process.